Memory integrity is a critical factor that distinguishes industrial control systems from general purpose computer systems. Memory errors, which affect memory integrity, are a significant concern in control system applications because they may affect an operation being controlled. For example, control programs and input/output (I/O) decisions are typically stored in RAM and precisely direct physical operations of the system. If an input bit were to suddenly change due to a memory error, the control program may react to the changed input by turning on or off a key output in response thereto. Depending on the nature of the output change, undesirable consequences may occur. Likewise, if a control program bit were to change unpredictably, the industrial controller may execute a random and/or unpredictable control sequence—this again may lead to undesirable control results. Thus, for robust control systems design, memory error detecting systems are generally necessary to ensure memory integrity.
In general, industrial controllers (e.g., Programmable Logic Controllers (PLCs), and Small Logic Controllers (SLCs)) provide parity and/or error check and correcting ECC systems to help ensure reliability of memory systems which control industrial processes. Parity bits allow for error detection of inadvertent changes in one or more bits of stored data. Parity may be provided as an extra bit of storage per byte of data written to memory, for example. Thus, for a controller employing eight-bit memory devices, nine bits of storage are required for each memory address.
In an ECC based system, codes (e.g., multiple bits) are computed and stored in conjunction with desired data. If an error is detected when memory is read, correcting algorithms are applied to the faulty data in conjunction with stored ECC codes, and in some cases, data may be restored. One such class of ECC correcting algorithms include utilization of “Hamming Codes” which are employed to detect and correct errors that may have occurred.
Traditionally, static random access memory (SRAM) systems have been employed by industrial controllers due in part to ease of parity implementation, and that 9 and 18 bit devices were readily available. Industrial controllers, however, would benefit greatly if commercial memory devices could be utilized such as for example synchronous dynamic random access memory (SDRAM) devices. This benefit is due in part to higher densities and lower costs than associated with conventional SRAM systems. Unfortunately, SDRAMs do not support parity due to cost pressures related to commercial PC markets. Additionally, SDRAMs do not readily support ECC due to the synchronous nature of the devices. In particular, synchronous memory devices which have been started on a sequential stream of accesses, do not lend themselves to stopping and correcting errors on the fly.
Consequently, there is a strong need in the art for a system and/or method for employing SDRAM technology in conjunction with industrial control systems. Moreover, there is a strong need for an ECC system which operates with SDRAMs and/or other memory systems to alleviate the aforementioned problems associated with conventional systems and/or methods.